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Disambiguation of "Tang, Qianying"

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A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer.

, , , and . A-SSCC, page 187-190. IEEE, (2018)

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Other publications of authors with the same name

A robot path planning approach based on generalized semi-infinite optimization., , and . RAM, page 768-773. IEEE, (2004)Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design., , , , , and . IEEE Micro, 34 (6): 74-85 (2014)Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis., , , and . JETC, 13 (1): 9:1-9:25 (2016)Two-Dimensional Layout Migration by Soft Constraint Satisfaction., and . ISQED, page 35-39. IEEE Computer Society, (2005)A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer., , , and . A-SSCC, page 187-190. IEEE, (2018)True Random Number Generator circuits based on single- and multi-phase beat frequency detection., , , , and . CICC, page 1-4. IEEE, (2014)A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC., , , , and . ISCAS, page 1-5. IEEE, (2018)An Efficient Method to Estimate Labelled Sample Size for Transductive LDA(QDA/MDA) Based on Bayes Risk., , , and . ECML, volume 3201 of Lecture Notes in Computer Science, page 274-285. Springer, (2004)The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications., , , , and . IEEE Trans. VLSI Syst., 23 (2): 280-291 (2015)Calligrapher: a new layout-migration engine for hard intellectual property libraries., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (9): 1347-1361 (2005)