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Disambiguation of "Egawa, Ryusuke"

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An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches.

, , , , and . IEEE Trans. Multi-Scale Computing Systems, 4 (4): 593-604 (2018)

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Other publications of authors with the same name

A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications., , , and . DSD, page 412-415. IEEE Computer Society, (2010)A Utility-Based Double Auction Mechanism for Efficient Grid Resource Allocation., , , and . ISPA, page 252-260. IEEE Computer Society, (2008)A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers., , , , and . 3DIC, page 1-6. IEEE, (2011)Cache partitioning strategies for 3-D stacked vector processors., , , and . 3DIC, page 1-6. IEEE, (2010)Scaling Up Of Wave Pipelines., , , and . VLSI Design, page 439-445. IEEE Computer Society, (2001)An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches., , , , and . IEEE Trans. Multi-Scale Computing Systems, 4 (4): 593-604 (2018)A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts., , , and . IEICE Transactions, 96-D (9): 2047-2054 (2013)An energy-efficient dynamic memory address mapping mechanism., , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2015)An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches., , , and . COOL Chips, page 1-2. IEEE Computer Society, (2017)Vertically integrated processor and memory module design for vector supercomputers., , , and . 3DIC, page 1-6. IEEE, (2013)