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HORNET: A Cycle-Level Multicore Simulator.

, , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (6): 890-903 (2012)

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Diastolic arrays: throughput-driven reconfigurable computing., , , , and . ICCAD, page 457-464. IEEE Computer Society, (2008)Deadlock-free fine-grained thread migration., , , , and . NOCS, page 33-40. ACM/IEEE Computer Society, (2011)Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine., , , , and . ICCD, page 145-153. IEEE Computer Society, (2013)Scalable, accurate multicore simulation in the 1000-core era., , , , , , and . ISPASS, page 175-185. IEEE Computer Society, (2011)Static virtual channel allocation in oblivious routing., , , , , , and . NOCS, page 38-43. IEEE Computer Society, (2009)HORNET: A Cycle-Level Multicore Simulator., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (6): 890-903 (2012)Memory coherence in the age of multicores., , , and . ICCD, page 1-8. IEEE Computer Society, (2011)Application-aware deadlock-free oblivious routing., , , , , and . ISCA, page 208-219. ACM, (2009)Optimal and Heuristic Application-Aware Oblivious Routing., , , , , and . IEEE Trans. Computers, 62 (1): 59-73 (2013)Oblivious Routing in On-Chip Bandwidth-Adaptive Networks., , , , , and . PACT, page 181-190. IEEE Computer Society, (2009)