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Disambiguation of "Gaillardon, Pierre-Emmanuel"

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Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.

, , , , and . ISCAS, page 2127-2130. IEEE, (2013)

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Pierre Nacke University of Stuttgart

Dr. rer. nat. Pierre Eckold University of Stuttgart

Pierre Kuna University of Stuttgart

 

Other publications of authors with the same name

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)GMS: Generic memristive structure for non-volatile FPGAs., , , , and . VLSI-SoC, page 94-98. IEEE, (2012)Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors., and . VLSI-SoC, page 107-112. IEEE, (2018)Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design., , , , , , and . IEEE Trans. on Circuits and Systems, 61-I (11): 3155-3164 (2014)Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection., , , and . NANOARCH, page 163-168. IEEE Computer Society/ACM, (2014)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors., , , , , , and . NANOARCH, page 55-60. ACM, (2012)Emerging reconfigurable nanotechnologies: can they support future electronics?, , , , , , , and . ICCAD, page 13. ACM, (2018)Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains., , , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 131-136. ACM, (2017)Multiple Independent Gate FETs: How many gates do we need?, , , , and . ASP-DAC, page 243-248. IEEE, (2015)Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop., , , , , , and . ISCAS, page 1-4. IEEE, (2017)