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Disambiguation of "Navabi, Zainalabedin"

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Facilitating testability of TLM FIFO: SystemC implementations.

, , , and . EWDTS, page 428-431. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching., , and . PDPTA, page 819-823. CSREA Press, (2003)Configurable architecture for memory BIST., , and . EWDTS, page 1-5. IEEE Computer Society, (2011)Generating test patterns for sequential circuits using random patterns by PLI functions., , , , and . EWDTS, page 456-461. IEEE Computer Society, (2010)Facilitating testability of TLM FIFO: SystemC implementations., , , and . EWDTS, page 428-431. IEEE Computer Society, (2010)Code optimization for enhancing SystemC simulation time., , , and . EWDTS, page 431-434. IEEE Computer Society, (2010)ESL design methodology for architecture exploration., and . EWDTS, page 395-401. IEEE Computer Society, (2010)Architecture design and technical methodology for bus testing., and . EWDTS, page 504-509. IEEE Computer Society, (2010)Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing., , and . VLSI-SOC, page 215-220. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Processor Testing Using an ADL Description and Genetic Algorithms., , , and . VLSI-SOC, page 186-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)A Flow Graph Technique for DFT Controller Modification., , , , and . SoCC, page 55-60. IEEE, (2005)