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Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor., , , , and . FPL, page 57-64. IEEE, (2005)Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor., , , , , and . FCCM, page 311-. IEEE Computer Society, (2002)The Design of the Amalgam Reconfigurable Cluster., , , , , and . FCCM, page 309-310. IEEE Computer Society, (2002)Vision for cross-layer optimization to address the dual challenges of energy and reliability., , and . DATE, page 1017-1022. IEEE, (2010)A magnetoelectronic macrocell employing reconfigurable threshold logic., and . FPGA, page 143-151. ACM, (2004)The M-Machine multicomputer., , , , , , and . MICRO, page 146-156. ACM / IEEE Computer Society, (1995)Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor., , , , , and . ISCA, page 306-317. IEEE Computer Society, (1998)An Efficient, Protected Message Interface., , , , and . IEEE Computer, 31 (11): 69-75 (1998)A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor., , , , and . Microprocessors and Microsystems, 31 (2): 146-159 (2007)Conversion of the Haydn symphonies into electronic form using automatic score recognition: a pilot study.. Document Recognition, volume 2181 of SPIE Proceedings, page 279-290. SPIE, (1994)