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Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies.

, , , and . DATE, page 202-207. IEEE Computer Society, (2004)

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Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (8): 1439-1452 (2008)Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications., and . CODES+ISSS, page 294-299. ACM, (2006)Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (4): 554-567 (2009)Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (3): 461-465 (2009)Data Reuse Driven Memory and Network-On-Chip Co-Synthesis., and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 299-312. Springer, (2007)FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations, and . CoRR, (2007)Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications., , , , and . IEEE Trans. VLSI Syst., 17 (9): 1343-1347 (2009)A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures., , and . ASP-DAC, page 328-333. IEEE, (2008)FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations., and . DATE, page 808-813. IEEE Computer Society, (2005)Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies., , , and . DATE, page 202-207. IEEE Computer Society, (2004)