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Disambiguation of "Lahiri, Kanishka"

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Design space exploration for optimizing on-chip communication architectures.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (6): 952-961 (2004)

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Other publications of authors with the same name

Variation-Tolerant Dynamic Power Management at the System-Level., , , and . IEEE Trans. VLSI Syst., 17 (9): 1220-1232 (2009)Fast performance analysis of bus-based system-on-chip communication architectures., , and . ICCAD, page 566-573. IEEE Computer Society, (1999)Communication architecture based power management for battery efficient system design., , and . DAC, page 691-696. ACM, (2002)Fast system-level power profiling for battery-efficient system design., , and . CODES, page 157-162. ACM, (2002)Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models., , , and . VLSI Design, page 579-585. IEEE Computer Society, (2005)Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis., , and . VLSI Design, page 513-520. IEEE Computer Society, (2007)Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends., , , , and . VLSI Design, page 8. IEEE Computer Society, (2007)Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures., , and . VLSI Design, page 29-35. IEEE Computer Society, (2001)Battery Life Estimation of Mobile Embedded Systems., , , , , and . VLSI Design, page 57-63. IEEE Computer Society, (2001)Battery-efficient architecture for an 802.11 MAC processor., , and . ICC, page 669-674. IEEE, (2002)