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Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: evaluation by large-scale real data.

S. Takitoh, S. Fujii, Y. Mase, J. Takasaki, T. Yamazaki, Y. Ohnishi, M. Yanagisawa, Y. Nakamura, and N. Kamatani. Bioinformatics, 23 (4): 408-413 (2007)

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MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.S. ya Abe, Y. Shi, M. Yanagisawa, and N. Togawa. IEICE Electronic Express, 9 (17): 1414-1422 (2012)A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration.K. Terada, M. Yanagisawa, and N. Togawa. ISCAS, page 2129-2132. IEEE, (2015)An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.N. Togawa, K. Hagi, M. Yanagisawa, and T. Ohtsuki. ASP-DAC, page 519-526. IEEE, (1998)Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories.T. Kojo, M. Tawada, M. Yanagisawa, and N. Togawa. ICCAD, page 682-689. IEEE, (2015)State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit.Y. Atobe, Y. Shi, M. Yanagisawa, and N. Togawa. APCCAS, page 607-610. IEEE, (2012)Scan-based attack against Trivium stream cipher independent of scan structure.M. Fujishiro, M. Yanagisawa, and N. Togawa. ASICON, page 1-4. IEEE, (2013)A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures.K. Igawa, Y. Shi, M. Yanagisawa, and N. Togawa. SoCC, page 7-12. IEEE, (2015)A delay variation and floorplan aware high-level synthesis algorithm with body biasing.K. Igawa, Y. Shi, M. Yanagisawa, and N. Togawa. ISQED, page 75-80. IEEE, (2016)Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures.H. Jiang, M. Fujishiro, H. Kodera, M. Yanagisawa, and N. Togawa. IEICE Transactions, 98-A (12): 2547-2555 (2015)A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches.M. Tawada, M. Yanagisawa, and N. Togawa. IEICE Transactions, 96-A (6): 1283-1292 (2013)