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Improving multiprocessor performance with fine-grain coherence bypass.

H. Wang, R. Wang, Z. Luan, X. Qian, and D. Qian. SCIENCE CHINA Information Sciences, 58 (1): 1-15 (2015)

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Qian Song University of Stuttgart

Qian Zhou University of Stuttgart

Qian Du University of Stuttgart

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Circuit implementation of floating point range reduction for trigonometric functions.X. Qian, H. Zhang, J. Yang, H. Huang, J. Zhang, and D. Fan. ISCAS, page 3010-3013. IEEE, (2007)Non-structured DNN Weight Pruning Considered Harmful.Y. Wang, S. Ye, Z. He, X. Ma, L. Zhang, S. Lin, G. Yuan, S. Tan, Z. Li, D. Fan and 3 other author(s). CoRR, (2019)ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multipliers.A. Ren, T. Zhang, S. Ye, J. Li, W. Xu, X. Qian, X. Lin, and Y. Wang. CoRR, (2018)E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGAs.Z. Li, C. Ding, S. Wang, W. Wen, Y. Zhuo, C. Liu, Q. Qiu, W. Xu, X. Lin, X. Qian and 1 other author(s). HPCA, page 69-80. IEEE, (2019)CSE: Parallel Finite State Machines with Convergence Set Enumeration.Y. Zhuo, J. Cheng, Q. Luo, J. Zhai, Y. Wang, Z. Luan, and X. Qian. MICRO, page 29-41. IEEE Computer Society, (2018)PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.L. Song, X. Qian, H. Li, and Y. Chen. HPCA, page 541-552. IEEE Computer Society, (2017)SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing.A. Ren, Z. Li, C. Ding, Q. Qiu, Y. Wang, J. Li, X. Qian, and B. Yuan. ASPLOS, page 405-418. ACM, (2017)Distributed Graph Processing System and Processing-in-memory Architecture with Precise Loop-carried Dependency Guarantee.Y. Zhuo, J. Chen, G. Rao, Q. Luo, Y. Wang, H. Yang, D. Qian, and X. Qian. ACM Trans. Comput. Syst., 37 (1-4): 5:1-5:37 (2021)SpeedyBox: Low-Latency NFV Service Chains with Cross-NF Runtime Consolidation.Y. Jiang, Y. Cui, W. Wu, Z. Xu, J. Gu, K. Ramakrishnan, Y. He, and X. Qian. ICDCS, page 68-79. IEEE, (2019)Squeezing out All the Value of Loaded Data: An Out-of-core Graph Processing System with Reduced Disk I/O.Z. Ai, M. Zhang, Y. Wu, X. Qian, K. Chen, and W. Zheng. USENIX Annual Technical Conference, page 125-137. USENIX Association, (2017)

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Disambiguation of "Qian, Xuehai"

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Improving multiprocessor performance with fine-grain coherence bypass.

Please choose a person to relate this publication to

Qian Song University of Stuttgart

Qian Zhou University of Stuttgart

Qian Du University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Qian, Xuehai"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Improving multiprocessor performance with fine-grain coherence bypass.

Please choose a person to relate this publication to

Qian Song University of Stuttgart

Qian Zhou University of Stuttgart

Qian Du University of Stuttgart

Other publications of authors with the same name

Disambiguation

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Chicago
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Improving multiprocessor performance with fine-grain coherence bypass.