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Test Compression Improvement with EDT Channel Sharing in SoC Designs.

Y. Huang, M. Kassab, J. Jahangiri, J. Rajski, W. Cheng, D. Han, J. Kim, and K. Chung. NATW, page 22-31. IEEE, (2014)

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On Linear Dependencies in Subspaces of LFSR-Generated Sequences.J. Rajski, and J. Tyszer. IEEE Trans. Computers, 45 (10): 1212-1216 (1996)High Performance Dense Ring Generators.G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer. IEEE Trans. Computers, 55 (1): 83-87 (2006)Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.J. Rajski, M. Potkonjak, A. Singh, A. Chatterjee, Z. Navabi, M. Guthaus, and S. Gören. VLSI-SoC, IEEE, (2013)Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.G. Mrugalski, J. Tyszer, and J. Rajski. VTS, page 377-388. IEEE Computer Society, (2000)A self-driven test structure for pseudorandom testing of non-scan sequential circuits.F. Muradali, and J. Rajski. VTS, page 17-25. IEEE Computer Society, (1996)Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.J. Rajski, G. Mrugalski, and J. Tyszer. VTS, page 236-245. IEEE Computer Society, (1999)Design of Phase Shifters for BIST Applications.J. Rajski, and J. Tyszer. VTS, page 218-224. IEEE Computer Society, (1998)Delay Fault Diagnosis Using Timing Information.Z. Wang, M. Marek-Sadowska, K. Tsai, and J. Rajski. ISQED, page 485-490. IEEE Computer Society, (2004)N-distinguishing Tests for Enhanced Defect Diagnosis.G. Chen, J. Rajski, S. Reddy, and I. Pomeranz. Asian Test Symposium, page 183-186. IEEE Computer Society, (2009)Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.E. Moghaddam, J. Rajski, S. Reddy, and J. Janicki. Asian Test Symposium, page 267-272. IEEE Computer Society, (2011)

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Test Compression Improvement with EDT Channel Sharing in SoC Designs.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Test Compression Improvement with EDT Channel Sharing in SoC Designs.

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Test Compression Improvement with EDT Channel Sharing in SoC Designs.