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Deadlock-Free Message Routing in Multiprocessor Interconnection Networks.

, and . IEEE Trans. Computers, 36 (5): 547-553 (1987)

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VLSI Architecture: Past, Present, and Future., and . ARVLSI, page 232-241. IEEE Computer Society, (1999)The BlackWidow High-Radix Clos Network., , , and . ISCA, page 16-28. IEEE Computer Society, (2006)Evaluating the Imagine Stream Architecture., , , , and . ISCA, page 14-25. IEEE Computer Society, (2004)CMOS High-Speed I/Os - Present and Future., , , , , , and . ICCD, page 454-461. IEEE Computer Society, (2003)Comparing Reyes and OpenGL on a Stream Architecture., , , and . Graphics Hardware, page 47-56. The Eurographics Association, (2002)Elastic Buffer Flow Control for On-Chip Networks., and . IEEE Trans. Computers, 62 (2): 295-309 (2013)Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks.. IEEE Trans. Computers, 40 (9): 1016-1023 (1991)Deadlock-Free Message Routing in Multiprocessor Interconnection Networks., and . IEEE Trans. Computers, 36 (5): 547-553 (1987)A tracking clock recovery receiver for 4-Gbps signaling., , and . IEEE Micro, 18 (1): 25-27 (1998)The GPU Computing Era., and . IEEE Micro, 30 (2): 56-69 (2010)