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Disambiguation of "Barua, Rajeev"

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, , , , and . ISPDC, page 133-140. IEEE Computer Society, (2010)

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Other publications of authors with the same name

Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter., , , , , , and . IEEE Trans. Parallel Distrib. Syst., 26 (8): 2154-2163 (2015)Easy PRAM-Based High-Performance Parallel Programming with ICE., , and . IEEE Trans. Parallel Distrib. Syst., 29 (2): 377-390 (2018)Memory allocation for embedded systems with a compile-time-unknown scratch-pad size., , and . ACM Trans. Embedded Comput. Syst., 8 (3): 21:1-21:32 (2009)RL-Bin, Robust Low-overhead Binary Rewriter., , , , and . FEAST@CCS, page 17-22. ACM, (2017)A compiler-level intermediate representation based binary analysis and rewriting system., , , , , , and . EuroSys, page 295-308. ACM, (2013)Compiler Support for Scalable and Efficient Memory Systems., , , and . IEEE Trans. Computers, 50 (11): 1234-1247 (2001)The Sensitivity of Communication Mechanisms to Bandwidth and Latency., , , , and . HPCA, page 37-46. IEEE Computer Society, (1998)An Accurate Stack Memory Abstraction and Symbolic Analysis Framework for Executables., , , , , and . ICSM, page 90-99. IEEE Computer Society, (2013)Instruction-Cache Locking for Improving Embedded Systems Performance., and . ACM Trans. Embedded Comput. Syst., 14 (3): 53:1-53:25 (2015)A Stack Memory Abstraction and Symbolic Analysis Framework for Executables., , , , , and . ACM Trans. Softw. Eng. Methodol., 25 (2): 19:1-19:38 (2016)