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Disambiguation of "Meunier, Quentin L."

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Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures.

, , , , and . MCSoC, page 61-68. IEEE Computer Society, (2016)

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L. Ahlgrimm

Lambert Theisen University of Stuttgart

Annika Liebgott

Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classification, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
Automated reference-free assessment of MR image quality using an active learning approach: Comparison of Support Vector Machine versus Deep Neural Network classification, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)An easy-to-use image labeling platform for automatic Magnetic Resonance Image Quality Assessment, , , , , , and . Proceedings of the IEEE International Symposium on Biomedical Imaging (ISBI), Melbourne, Australia, (April 2017)Automated image quality assessment in whole-body MRI, , , , , , , , and . Proceedings of the Radiological Society of North America (RSNA), Chicago, USA, (November 2016)

Univ. -Prof. Dr. Remco Ingmar Leine University of Stuttgart

Christian León University of Stuttgart

 

Other publications of authors with the same name

Hardware/software support for adaptive work-stealing in on-chip multiprocessor., , and . Journal of Systems Architecture - Embedded Systems Design, 56 (8): 392-406 (2010)Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques., and . Technique et Science Informatiques, 30 (9): 1061-1087 (2011)Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles. (Study of two Solutions for Hardware Support of Parallel Programming in Integrated Multiprocessors: Work-Stealing and Transactional Memory).. Grenoble Institute of Technology, France, (2010)Executing secured virtual machines within a manycore architecture., , , and . Microprocessors and Microsystems - Embedded Hardware Design, (2017)Fixed-point accuracy evaluation in the context of conditional structures., , , and . EUSIPCO, page 1934-1938. IEEE, (2011)RWT: Suppressing Write-Through Cost When Coherence is Not Needed., , , , , and . ISVLSI, page 434-439. IEEE Computer Society, (2015)GECOS : Mécanisme de synchronisation passant à l'échelle à plusieurs lecteurs et un écrivain pour structures chaînées., , , and . Technique et Science Informatiques, 34 (1-2): 53-78 (2015)Modeling a Cache Coherence Protocol with the Guarded Action Language., , and . MARS/VPT@ETAPS, volume 268 of EPTCS, page 88-103. (2018)Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures., , , , , , , , and . DASIP, page 25-30. IEEE, (2018)Fixed-point accuracy evaluation in the context of conditional structures., , , and . EUSIPCO, page 1934-1938. IEEE, (2011)