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Lesion Detection, Segmentation and Prediction in Multiple Sclerosis Clinical Trials.

A. Doyle, C. Elliott, Z. Karimaghaloo, N. Subbanna, D. Arnold, and T. Arbel. BrainLes@MICCAI, volume 10670 of Lecture Notes in Computer Science, page 15-28. Springer, (2017)

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Dr. Andrew Clifton University of Stuttgart

Andrew Furze University of Stuttgart

Dr. Andrew Clark University of Stuttgart

Andrew Nelson Butterfield University of Stuttgart

Other publications of authors with the same name

A Survey of Crowdsourcing in Medical Image Analysis.S. Ørting, A. Doyle, M. Hirth, A. van Hilten, O. Inel, C. Madan, P. Mavridis, H. Spiers, and V. Cheplygina. CoRR, (2019)A Low-Cost, Semi-Autonomous Wheelchair Controlled by Motor Imagery and Jaw Muscle Activation.M. Xiong, A. Brandenberger, M. Bulger, W. Chien, A. Doyle, W. Hao, J. Jiang, K. Kim, S. Lahlou, C. Leung and 21 other author(s). SMC, page 2180-2185. IEEE, (2019)Predicting Future Disease Activity and Treatment Responders for Multiple Sclerosis Patients Using a Bag-of-Lesions Brain Representation.A. Doyle, D. Precup, D. Arnold, and T. Arbel. MICCAI (3), volume 10435 of Lecture Notes in Computer Science, page 186-194. Springer, (2017)Lesion Detection, Segmentation and Prediction in Multiple Sclerosis Clinical Trials.A. Doyle, C. Elliott, Z. Karimaghaloo, N. Subbanna, D. Arnold, and T. Arbel. BrainLes@MICCAI, volume 10670 of Lecture Notes in Computer Science, page 15-28. Springer, (2017)Benchmark on Automatic Six-Month-Old Infant Brain Segmentation Algorithms: The iSeg-2017 Challenge.L. Wang, D. Nie, G. Li, É. Puybareau, J. Dolz, Q. Zhang, F. Wang, J. Xia, Z. Wu, J. Chen and 19 other author(s). IEEE Trans. Med. Imaging, 38 (9): 2219-2230 (2019)Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End.J. Zhuang, B. Doyle, and E. Fang. IEEE Trans. on Circuits and Systems, 58-II (5): 289-293 (2011)An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.A. Loke, B. Doyle, S. Maheshwari, D. Fischette, C. Wang, T. Wee, and E. Fang. J. Solid-State Circuits, 47 (11): 2627-2642 (2012)A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.D. Fischette, A. Loke, M. Oshima, B. Doyle, R. Bakalski, R. DeSantis, A. Thiruvengadam, C. Wang, G. Talbot, and E. Fang. ISSCC, page 246-247. IEEE, (2010)Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links.A. Loke, B. Doyle, M. Oshima, W. Williams, R. Lewis, C. Wang, A. Hanpachern, K. Tucker, P. Gurunath, G. Asada and 3 other author(s). CICC, page 605-608. IEEE, (2009)