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Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-Based Applications.

, , , , and . SBAC-PAD, page 57-64. IEEE, (2018)

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Computational reflection and its application to platform verification., , and . Design Autom. for Emb. Sys., 16 (1): 1-17 (2012)A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (11): 1319-1328 (2001)Data center power and performance optimization through global selection of P-states and utilization rates., , , , and . SUSCOM, 2 (4): 198-208 (2012)Approximation with Error Bounds in Spark., , , and . CoRR, (2018)A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 123-129. IEEE Computer Society, (2007)An early real-time checker for retargetable compile-time analysis., , , and . SBCCI, ACM, (2009)The ArchC Architecture Description Language and Tools., , , , , and . International Journal of Parallel Programming, 33 (5): 453-484 (2005)Optimal Live Range Merge for Address Register Allocation in Embedded Programs., , , , and . CC, volume 2027 of Lecture Notes in Computer Science, page 274-288. Springer, (2001)Uncertainty Propagation in Data Processing Systems., , , , and . SoCC, page 95-106. ACM, (2018)Exploring Memory Hierarchy with ArchC., , , , and . SBAC-PAD, page 2-9. IEEE Computer Society, (2003)