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Disambiguation of "Piestrak, Stanislaw J."

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Fault-aware configurable logic block for reliable reconfigurable FPGAs.

, , and . ISCAS, page 2732-2735. IEEE, (2015)

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J. K\"astner

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Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor., , and . IEEE Trans. Computers, 62 (6): 1179-1192 (2013)On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.. DSD, page 133-140. IEEE Computer Society, (2010)The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes.. FTCS, page 457-464. IEEE Computer Society, (1990)Design of cost-efficient multipliers modulo 2a-1.. ISCAS, page 4093-4096. IEEE, (2010)Design of Reverse Converters for a New Flexible RNS Five-Moduli Set 2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1 (n Even)., and . CSSP, 36 (11): 4593-4614 (2017)Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels., and . Signal Processing Systems, 90 (3): 323-339 (2018)Error recovery technique for coarse-grained reconfigurable architectures., , , and . DDECS, page 441-446. IEEE Computer Society, (2011)Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.. IEEE Trans. Computers, 39 (3): 360-374 (1990)The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.. IEEE Trans. Computers, 42 (6): 700-712 (1993)Design of the coarse-grained reconfigurable architecture DART with on-line error detection., , , and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (2): 124-136 (2014)