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Disambiguation of "Li, Shuangchen"

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FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.

, , , , , , , and . ASPLOS, page 733-747. ACM, (2019)

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M.Sc. Yunxuan Li University of Stuttgart

Yu Li University of Stuttgart

Jie Li University of Stuttgart

Zheng Li University of Stuttgart

Li Zhong University of Stuttgart

 

Other publications of authors with the same name

PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors., , , , , , , , and . IEEE Trans. VLSI Syst., 22 (7): 1491-1505 (2014)Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications., , , , , , and . ASP-DAC, page 225-230. IEEE, (2013)Nonvolatile memory allocation and hierarchy optimization for high-level synthesis., , , , and . ASP-DAC, page 166-171. IEEE, (2015)Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory., , , , and . DATE, page 800-805. IEEE, (2019)Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing., , , , and . AsianHOST, page 74-79. IEEE, (2018)Boosting Deep Neural Network Efficiency with Dual-Module Inference., , , , , , , , , and . ICML, volume 119 of Proceedings of Machine Learning Research, page 6205-6215. PMLR, (2020)AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory., , , , , and . DATE, page 625-628. IEEE, (2018)SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator., , , , , , , , and . MICRO, page 696-709. IEEE Computer Society, (2018)AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip., , , , , , , , and . ASP-DAC, page 146-151. ACM, (2019)Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators., , , , , , , , , and 1 other author(s). ISLPED, page 1-6. IEEE, (2019)