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Disambiguation of "Stergiou, Stergios"

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Timing-Error-Tolerant Network-on-Chip Design Methodology.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (7): 1297-1310 (2007)

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Other publications of authors with the same name

A fast and efficient heuristic ESOP minimization algorithm., , and . ACM Great Lakes Symposium on VLSI, page 78-81. ACM, (2004)A Multi-Lingual Synthesis and Verification Environment., , , and . DSD, page 8-15. IEEE Computer Society, (2001)Timing-Error-Tolerant Network-on-Chip Design Methodology., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (7): 1297-1310 (2007)Set Cover at Web Scale., and . KDD, page 1125-1133. ACM, (2015)ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips., , , , , and . DATE, page 1188-1193. IEEE Computer Society, (2005)xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips., , , , , and . DATE, page 1188-1193. IEEE Computer Society, (2005)Shortcutting Label Propagation for Distributed Connected Components., , and . WSDM, page 540-546. ACM, (2018)Dynamically resizable binary decision diagrams., and . ACM Great Lakes Symposium on VLSI, page 185-190. ACM, (2010)Optimizing BDDs for time-series dataset manipulation., and . DATE, page 1018-1021. EDA Consortium San Jose, CA, USA / ACM DL, (2013)NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip., , , , , , and . IEEE Trans. Parallel Distrib. Syst., 16 (2): 113-129 (2005)