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Corner block list representation and its application with boundary constraints., , , , , and . Science in China Series F: Information Sciences, 47 (1): 1-19 (2004)Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization., , , , and . IEEE Trans. VLSI Syst., 20 (11): 2143-2147 (2012)Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs., , , , , and . Integration, 46 (1): 1-9 (2013)Incremental power optimization for multiple supply voltage design., , , and . ISQED, page 280-286. IEEE Computer Society, (2009)Automatic enhanced CDFG generation based on runtime instrumentation., , , and . CSCWD, page 92-97. IEEE, (2013)LP based white space redistribution for thermal via planning and performance optimization in 3D ICs., , , , and . ASP-DAC, page 209-212. IEEE, (2008)Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs., , , , , and . ASP-DAC, page 261-266. IEEE, (2011)A buffer planning algorithm for chip-level floorplanning., , , , , , and . Science in China Series F: Information Sciences, 47 (6): 763-776 (2004)Shift-based Primitives for Efficient Convolutional Neural Networks., , , and . CoRR, (2018)VLSI floorplanning with boundary constraints based on corner block list., , , , , and . ASP-DAC, page 509-514. ACM, (2001)