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Test Data Compression for System-on-a-Chip Using Golomb Codes.

, and . VTS, page 113-120. IEEE Computer Society, (2000)

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Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression., and . VTS, page 42-47. IEEE Computer Society, (2001)Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction., , and . VTS, page 84-92. IEEE Computer Society, (2007)Special session 11B: Hot topic on-chip clocking - Industrial trends.. VTS, page 1. IEEE Computer Society, (2013)Scalable Adaptive Scan (SAS)., , and . DATE, page 1476-1481. IEEE, (2009)Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression., and . DATE, page 598-603. IEEE Computer Society, (2002)A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design., and . DFT, page 511-518. IEEE Computer Society, (2003)Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes., , , and . IEEE Trans. Instrumentation and Measurement, 55 (2): 389-399 (2006)Proactive management of X's in scan chains for compression., , and . ISQED, page 260-265. IEEE Computer Society, (2009)Interval Based X-Masking for Scan Compression Architectures., and . ISQED, page 821-826. IEEE Computer Society, (2008)Designing effective scan compression solutions for industrial circuits., , and . ISQED, page 167-172. IEEE, (2015)