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Early SoC security validation by VP-based static information flow analysis.

, , , , and . ICCAD, page 400-407. IEEE, (2017)

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ParCoSS: Efficient Parallelized Compiled Symbolic Simulation., , , and . CAV (2), volume 9780 of Lecture Notes in Computer Science, page 177-183. Springer, (2016)Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction., , , and . STTT, 21 (5): 545-565 (2019)Extensible and Configurable RISC-V Based Virtual Prototype., , , and . FDL, page 5-16. IEEE, (2018)Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules., , , and . ATVA, volume 9364 of Lecture Notes in Computer Science, page 228-233. Springer, (2015)Verifying SystemC using an intermediate verification language and symbolic simulation., , , and . DAC, page 116:1-116:6. ACM, (2013)Towards formal verification of real-world SystemC TLM peripheral models - a case study., , , and . DATE, page 1160-1163. IEEE, (2016)Compiled symbolic simulation for systemC., , , and . ICCAD, page 52. ACM, (2016)Towards fully automated TLM-to-RTL property refinement., , , and . DATE, page 1508-1511. IEEE, (2018)Towards Automated Refinement of TLM Properties to RTL., , , and . MBMV, Universität Tübingen, (2018)Maximizing power state cross coverage in firmware-based power management., , , and . ASP-DAC, page 335-340. ACM, (2019)