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Disambiguation of "Sasan, Avesta"

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Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification.

, , , , , and . DAC, page 1:1-1:6. ACM, (2018)

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History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring., , , , and . ISQED, page 498-505. IEEE, (2012)Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance., , and . Near Threshold Computing, Springer, (2016)Architectural considerations for FPGA acceleration of machine learning applications in MapReduce., , , , , and . SAMOS, page 89-96. ACM, (2018)A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)., , , and . CASES, page 251-260. ACM, (2009)Threats on Logic Locking: A Decade Later., , , and . ACM Great Lakes Symposium on VLSI, page 471-476. ACM, (2019)MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits., , , , , and . IEEE Trans. VLSI Syst., 19 (12): 2303-2316 (2011)A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews., , , and . ISVLSI, page 272-277. IEEE Computer Society, (2017)ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications., , , , , , , and . ICPP, page 7:1-7:11. ACM, (2019)Adversarial Attack on Microarchitectural Events based Malware Detectors., , , , , , , and . DAC, page 164. ACM, (2019)Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification., , , , , and . DAC, page 1:1-1:6. ACM, (2018)