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A communication model and partitioning algorithm for streaming applications for an embedded MPSoC.

, , , , , , , , and . ISSoC, page 1-6. IEEE, (2014)

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CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories., , , , , , , , and . IEEE Trans. Parallel Distrib. Syst., 29 (5): 1030-1043 (2018)Performance estimation of streaming applications for hierarchical MPSoCs., , , , , , , and . RAPIDO@HiPEAC, page 3:1-3:6. ACM, (2016)Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI., , , , , , , and . ISCAS, page 1925-1928. IEEE, (2015)System-Level Analysis of Network Interfaces for Hierarchical MPSoCs., , , , , and . NoCArc@MICRO, page 3-8. ACM, (2015)Design Space Exploration for Memory Subsystems of VLIW Architectures., , , and . NAS, page 377-385. IEEE Computer Society, (2010)A communication model and partitioning algorithm for streaming applications for an embedded MPSoC., , , , , , , , and . ISSoC, page 1-6. IEEE, (2014)Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications., , , , , and . NORCHIP, page 1-4. IEEE, (2013)Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen.. Bielefeld University, Germany, (2016)CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture., , , , and . EUC, page 9-16. IEEE Computer Society, (2014)Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI., , , , , , , and . MCSoC, page 175-181. IEEE Computer Society, (2015)