Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

On-Chip Test Generation Using Linear Subspaces., , and . European Test Symposium, page 111-116. IEEE Computer Society, (2006)Automatic error diagnosis and correction for RTL designs., , , and . HLDVT, page 65-72. IEEE Computer Society, (2007)Node Mergers in the Presence of Don't Cares., , , and . ASP-DAC, page 414-419. IEEE Computer Society, (2007)Circuit Placement., and . Encyclopedia of Algorithms, (2016)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)Min-cut floorplacement., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (7): 1313-1326 (2006)Benchmarking for large-scale placement and beyond., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (4): 472-487 (2004)Getting Your Bits in Order.. IEEE Design & Test of Computers, 28 (4): 98-101 (2011)Simulation of Quantum Circuits via Stabilizer Frames., and . IEEE Trans. Computers, 64 (8): 2323-2336 (2015)Circuit CAD Tools as a Security Threat., , and . HOST, page 65-66. IEEE Computer Society, (2008)