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High speed ASIC implementations of leakage-resilient cryptography., , , , , and . DATE, page 1259-1264. IEEE, (2018)Transparent Memory Encryption and Authentication., , , , and . IACR Cryptology ePrint Archive, (2017)Pointing in the Right Direction - Securing Memory Accesses in a Faulty World., , , and . ACSAC, page 595-604. ACM, (2018)ConTExT: Leakage-Free Transient Execution., , , , , and . CoRR, (2019)Leakage Bounds for Gaussian Side Channels., , , , , , and . CARDIS, volume 10728 of Lecture Notes in Computer Science, page 88-104. Springer, (2017)Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs., , , and . VMCAI, volume 11388 of Lecture Notes in Computer Science, page 183-204. Springer, (2019)SecWalk: Protecting Page Table Walks Against Fault Attacks., , , and . HOST, page 56-67. IEEE, (2021)Protecting RISC-V Processors against Physical Attacks., , , and . DATE, page 1136-1141. IEEE, (2019)Securing conditional branches in the presence of fault attacks., , and . DATE, page 1586-1591. IEEE, (2018)Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS., , , , , and . CS2@HiPEAC, page 19-24. ACM, (2017)