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Disambiguation of "Karanth, Avinash"

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Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies.

, , , , , , , , and . T-SUSC, 4 (3): 293-307 (2019)

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Other publications of authors with the same name

RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture., and . ICCD, page 488-495. IEEE Computer Society, (2018)IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores., , , and . ISCA, page 589-600. ACM, (2019)Dynamic Voltage and Frequency Scaling to Improve Energy-Efficiency of Hardware Accelerators., and . HiPC, page 232-241. IEEE, (2021)Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs., , and . JETC, 15 (1): 4:1-4:16 (2019)Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques., , , , and . IEEE Trans. Computers, 68 (3): 375-389 (2019)High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin., , , and . DATE, page 1166-1171. IEEE, (2019)Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies., , , , , , , , and . T-SUSC, 4 (3): 293-307 (2019)Co-design of channel buffers and crossbar organizations in NoCs architectures., , , , and . ICCAD, page 219-226. IEEE Computer Society, (2011)Packet security with path sensitization for NoCs., and . DATE, page 1136-1139. IEEE, (2016)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures., , , and . ASP-DAC, page 1-6. IEEE, (2009)