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Disambiguation of "Mishchenko, Alan"

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Technology Mapping into General Programmable Cells.

, , , and . FPGA, page 70-73. ACM, (2015)

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Other publications of authors with the same name

Regular Realization of Symmetric Functions Using Reversible Logic., , , , , , , , , and . DSD, page 245-253. IEEE Computer Society, (2001)Mapping into LUT structures., , , , , and . DATE, page 1579-1584. IEEE, (2012)GLA: gate-level abstraction revisited., , , , , and . DATE, page 1399-1404. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Speculative reduction-based scalable redundancy identification., , , and . DATE, page 1674-1679. IEEE, (2009)Threshold Logic Synthesis Based on Cut Pruning., , , , and . ICCAD, page 494-499. IEEE, (2015)Synthesis for regularity using decision diagrams [logic IC synthesis and layout]., and . ISCAS (5), page 4721-4724. IEEE, (2005)Efficient FPGA Resynthesis Using Precomputed LUT Structures., , , , and . FPL, page 532-537. IEEE Computer Society, (2010)WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging., , , and . TRETS, 2 (2): 14:1-14:24 (2009)Reducing Multi-Valued Algebraic Operations to Binary., , and . IWLS, page 339-344. (2002)Logic Synthesis of Reversible Wave Cascades., and . IWLS, page 197-202. (2002)