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Disambiguation of "Bhattacharyya, Tarun Kanti"

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Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.

, , , and . VLSI Design, page 152-157. IEEE Computer Society, (2010)

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Arnab Bhattacharyya University of Stuttgart

Tarun Tater University of Stuttgart

Tarun Kumar Mitruka Vinod Kumar Mitruka University of Stuttgart

 

Other publications of authors with the same name

A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL., and . Microelectronics Journal, 44 (8): 649-657 (2013)A High Efficiency Body Injected Differential Power Amplifier at 2.4GHz for Low Power Applications., and . VLSI Design, page 208-213. IEEE Computer Society, (2018)Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC., and . ISVLSI, page 114-119. IEEE Computer Society, (2011)Efficient design technique for pulse swallow based fractional-N frequency divider., and . ISCAS, page 457-460. IEEE, (2015)Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops., and . Integration, (2018)Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver., , , and . VLSI Design, page 124-129. IEEE Computer Society, (2011)Fully Concurrent Dual-Band LNA Operating in 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver with Sub-2dB Noise Figure., , , and . ICETET, page 731-734. IEEE Computer Society, (2010)A New Open Loop Linearization Technique for Power Amplifier Circuit in MMIC for 5G Wireless Backhaul Application., and . TENCON, page 2116-2121. IEEE, (2018)A 10-b, 500 MSPS current steering CMOS DAC with a switching current cell and high SFDR value., and . APCCAS, page 113-116. IEEE, (2014)Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors., , , and . VLSI Design, page 185-190. IEEE Computer Society, (2012)