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Modeling avalanche breakdown for ESD diodes in integrated circuits.

C. Stefanucci, P. Buccella, M. Kayal, and J. Sallese. DTIS, page 1-3. IEEE, (2015)

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Modeling parasitic vertical PNP in HVCMOS.C. Stefanucci, P. Buccella, M. Kayal, and J. Sallese. MIXDES, page 486-489. IEEE, (2015)Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics.C. Rossi, P. Buccella, C. Stefanucci, and J. Sallese. NEWCAS, page 35-39. IEEE, (2018)Modeling avalanche breakdown for ESD diodes in integrated circuits.C. Stefanucci, P. Buccella, M. Kayal, and J. Sallese. DTIS, page 1-3. IEEE, (2015)Spice simulation of passive protection in smart power ICs.P. Buccella, C. Stefanucci, J. Sallese, and M. Kayal. MIXDES, page 500-503. IEEE, (2015)Substrate noise modeling with dedicated CAD framework for smart power ICs.H. Zou, Y. Moursy, R. Iskander, C. Stefanucci, P. Buccella, M. Kayal, and J. Sallese. ISCAS, page 1554-1557. IEEE, (2015)Active guard ring characterization for Smart Power ICs.P. Buccella, C. Stefanucci, J. Sallese, and M. Kayal. MIXDES, page 305-309. IEEE, (2016)Spice simulation of substrate minority carriers propagation with equivalent electrical circuit.P. Buccella, C. Stefanucci, J. Sallese, and M. Kayal. MIXDES, page 347-350. IEEE, (2014)Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs.P. Buccella, C. Stefanucci, H. Zou, Y. Moursy, R. Iskander, J. Sallese, and M. Kayal. IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (9): 1489-1502 (2016)Analysis of substrate currents propagation in HVCMOS technology.C. Stefanucci, P. Buccella, E. Seebacher, A. Steinmair, M. Kayal, and J. Sallese. ESSDERC, page 319-322. IEEE, (2016)Optimization strategy of numerical simulations applied to EPFL substrate model.C. Stefanucci, P. Buccella, M. Kayal, and J. Sallese. MIXDES, page 334-337. IEEE, (2014)

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Modeling avalanche breakdown for ESD diodes in integrated circuits.

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Disambiguation of "Buccella, Pietro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Modeling avalanche breakdown for ESD diodes in integrated circuits.

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Modeling avalanche breakdown for ESD diodes in integrated circuits.