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Disambiguation of "e Silva, Luís Guerra"

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Variation-Aware, Library Compatible Delay Modeling Strategy.

, , , and . VLSI-SoC, page 122-127. IEEE, (2006)

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E. Garrelts

E. Zafeiriou

Luis Orozco University of Stuttgart

Luis Mandl University of Stuttgart

Prof. Jose Luis Moro University of Stuttgart

 

Other publications of authors with the same name

Efficient computation of the worst-delay corner., , and . DATE, page 1617-1622. EDA Consortium, San Jose, CA, USA, (2007)Grid-based statistical timing analysis., and . IADIS AC, page 73-80. IADIS, (2005)Effective Corner-Based Techniques for Variation-Aware IC Timing Verification., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (1): 157-162 (2010)Library Compatible Variational Delay Computation., , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 157-176. Springer, (2006)Solving Satisfiability in Combinational Circuits., and . IEEE Design & Test of Computers, 20 (4): 16-21 (2003)Algorithms for Solving Boolean Satisfiability in Combinational Circuits., , and . DATE, page 526-530. IEEE Computer Society / ACM, (1999)TAU 2013 variation aware timing analysis contest., , , , , and . ISPD, page 171-178. ACM, (2013)Speedpath analysis under parametric timing models., , and . DAC, page 268-273. ACM, (2010)Unifying functional and parametric timing verification.. ACM Great Lakes Symposium on VLSI, page 135-140. ACM, (2012)Variation-Aware, Library Compatible Delay Modeling Strategy., , , and . VLSI-SoC, page 122-127. IEEE, (2006)