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Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.

, , , , , and . ICS, page 179-188. ACM, (2005)

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Optimizing the Instruction Cache Performance of the Operating System., , and . IEEE Trans. Computers, 47 (12): 1363-1381 (1998)Optimization of Instruction Fetch for Decision Support Workloads., , , , , and . ICPP, page 238-245. IEEE Computer Society, (1999)Facelift: Hiding and slowing down aging in multicores., and . MICRO, page 129-140. IEEE Computer Society, (2008)Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing., , , and . MICRO, page 27-42. IEEE Computer Society, (2007)AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection., , and . MICRO, page 287-297. IEEE Computer Society, (2010)An efficient algorithm for the run-time parallelization of DOACROSS loops., , and . SC, page 518-527. IEEE Computer Society, (1994)Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors., , and . HPCA, page 135-139. IEEE Computer Society, (1999)Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors., , and . HPCA, page 162-173. IEEE Computer Society, (1998)Speeding up the Memory Hierarchy in Flat COMA Multiprocessors., and . HPCA, page 4-13. IEEE Computer Society, (1997)Extreme-scale computer architecture: Energy efficiency from the ground up‡.. DATE, page 1-5. European Design and Automation Association, (2014)