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Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.

, , and . Signal Processing Systems, 52 (1): 13-34 (2008)

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Prolog to the Section on Hardware/Software Codesign.. Proceedings of the IEEE, 100 (Centennial-Issue): 1409-1410 (2012)Overcoming performance bottlenecks in using OpenMP on SMP clusters., , , and . Parallel Computing, 34 (10): 570-592 (2008)Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing., , and . ICPP, page 122-127. IEEE Computer Society, (1997)An efficient parallel motion estimation algorithm and X264 parallelization in CUDA., , and . DASIP, page 91-98. IEEE, (2011)Pipelined data parallel task mapping/scheduling technique for MPSoC., and . DATE, page 69-74. IEEE, (2009)Optimized Timed Hardware Software Cosimulation without Roll-back., and . DATE, page 945-946. IEEE Computer Society, (1998)A Hardware Software Cosimulation Backplane with Automatic Interface Generation., and . ASP-DAC, page 177-182. IEEE, (1998)An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems., , , , , and . RTSS, page 363-372. IEEE Computer Society, (2012)An Application Framework for Loosely Coupled Networked Cyber-Physical Systems., , , and . EUC, page 144-153. IEEE Computer Society, (2010)Automatic CUDA Code Synthesis Framework for Multicore CPU and GPU Architectures., , and . PPAM (1), volume 7203 of Lecture Notes in Computer Science, page 579-588. Springer, (2011)