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Disambiguation of "Ku, Ja Chun"

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On the Scaling of Temperature-Dependent Effects.

, and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (10): 1882-1888 (2007)

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Phi-Long Chung University of Stuttgart

Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)

Sook Ja Schmitz University of Stuttgart

Farane Jalali Farahani University of Stuttgart

Pratibha Jakhar University of Stuttgart

 

Other publications of authors with the same name

A self-adjusting clock tree architecture to cope with temperature variations., , , and . ICCAD, page 75-82. IEEE Computer Society, (2007)SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation., , , and . IEEE Trans. VLSI Syst., 18 (9): 1323-1336 (2010)Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (2): 241-248 (2008)Thermal Management of On-Chip Caches Through Power Density Minimization., , , and . IEEE Trans. VLSI Syst., 15 (5): 592-604 (2007)The importance of including thermal effects in estimating the effectiveness of power reduction techniques., , and . CICC, page 301-304. IEEE, (2005)Variable latency caches for nanoscale processor., , , , and . SC, page 20. ACM Press, (2007)Power density minimization for highly-associative caches in embedded processors., , , and . ACM Great Lakes Symposium on VLSI, page 100-104. ACM, (2006)Thermal Management of On-Chip Caches Through Power Density Minimization., , , and . MICRO, page 283-293. IEEE Computer Society, (2005)Attaining Thermal Integrity in Nanometer Chips., and . ISCAS, page 3223-3226. IEEE, (2007)Thermal-aware methodology for repeater insertion in low-power VLSI circuits., and . ISLPED, page 86-91. ACM, (2007)