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Disambiguation of "Ghosh, Indradeep"

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WEAVE: WEb Applications Validation Environment.

, , , , , and . ICSE Companion, page 101-111. IEEE, (2009)

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Univ. -Prof. Dr. Robin Ghosh University of Stuttgart

Tufan Ghosh University of Stuttgart

Gautam Ghosh University of Stuttgart

 

Other publications of authors with the same name

High-level test synthesis: a survey., and . Integration, 26 (1-2): 79-99 (1998)A Technique for Identifying RTL and Gate-Level Correspondences., , , and . ICCD, page 591-594. IEEE Computer Society, (2000)Hierarchical test generation and design for testability methods for ASPPs and ASIPs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (3): 357-370 (1999)A design for testability technique for RTL circuits using control/data flow extraction., , and . ICCAD, page 329-336. IEEE Computer Society / ACM, (1996)High Level Design Validation: Current Practices and Future Directions., , , and . VLSI Design, page 9-11. IEEE Computer Society, (2004)On automatic generation of RTL validation test benches using circuit testing techniques., and . ACM Great Lakes Symposium on VLSI, page 289-294. ACM, (2003)VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images., and . IJPRAI, 9 (2): 449-462 (1995)High Level Test Generation for Custom Hardware: An Industrial Perspective.. Asian Test Symposium, page 458. IEEE Computer Society, (2005)Design for Verification at the Register Transfer Level., , and . VLSI Design, page 420-425. IEEE Computer Society, (2002)A BIST scheme for RTL circuits based on symbolic testabilityanalysis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (1): 111-128 (2000)