PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Kahng, Andrew B."

Author of the publication

copydeleteadd this publication to your clipboard
Toward quantifying the IC design value of interconnect technology improvements.

, , and . SLIP, page 1-6. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. Andrew Clifton University of Stuttgart

Grand challenges in the digitalisation of wind energy, , , , , , , , , and 1 other author(s). Wind energy science, 8 (6): 947-974 (2023)

B. Schlecht

Andrew Furze University of Stuttgart

Dr. Andrew Clark University of Stuttgart

Max B. Schäfer

 

Other publications of authors with the same name

Spectral Partitioning with Multiple Eigenvectors., , and . Discrete Applied Mathematics, 90 (1-3): 3-26 (1999)Statistical Timing Analysis in the Presence of Signal-Integrity Effects., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (10): 1873-1877 (2007)Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (7): 1070-1082 (2010)Fast Dual-Graph-Based Hotspot Filtering., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (9): 1635-1642 (2008)Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (8): 1229-1242 (2010)Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (3): 404-417 (2012)CMP Fill Synthesis: A Survey of Recent Studies., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (1): 3-19 (2008)The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap., , , and . ICCD, page 153-160. IEEE Computer Society, (2014)Optimal equivalent circuits for interconnect delay calculations using moments., and . EURO-DAC, page 164-169. IEEE Computer Society, (1994)Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay., and . EURO-DAC, page 440-445. IEEE Computer Society, (1994)