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Deep learning acceleration based on in-memory computing., , , , , , , , , and 7 other author(s). IBM Journal of Research and Development, 63 (6): 7:1-7:16 (2019)Applications of Computation-In-Memory Architectures based on Memristive Devices., , , , , , , , , and 3 other author(s). DATE, page 486-491. IEEE, (2019)In-memory hyperdimensional computing., , , , , and . CoRR, (2019)Computational memory-based inference and training of deep neural networks., , , , , , , , , and 6 other author(s). VLSI Circuits, page 168-. IEEE, (2019)A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks., , , , , , and . CoRR, (2022)4K Real-Time HEVC Decoder on an FPGA., , , , and . IEEE Trans. Circuits Syst. Video Techn., 26 (1): 236-249 (2016)XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks., , , , and . COOL CHIPS, page 1-3. IEEE Computer Society, (2018)High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension., , , , , , , , , and 1 other author(s). ASAP, page 164-169. IEEE Computer Society, (2017)