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Disambiguation of "ke Wang, Ze"

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A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT.

, , , and . IEEE Trans. VLSI Syst., 23 (5): 973-977 (2015)

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Ke Peng University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Dr. rer. nat. Lei Wang University of Stuttgart

Francesca Zermiani University of Stuttgart

 

Other publications of authors with the same name

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays., , , and . Journal of Zhejiang University - Science C, 12 (4): 323-329 (2011)A performance analysis framework for optimizing OpenCL applications on FPGAs., , , and . HPCA, page 114-125. IEEE Computer Society, (2016)Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application., , and . IEEE Trans. VLSI Syst., 24 (7): 2449-2461 (2016)A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT., , , and . IEEE Trans. VLSI Syst., 23 (5): 973-977 (2015)Improving Data Partitioning Performance on OpenCL-Based FPGAs., , and . FCCM, page 34. IEEE Computer Society, (2015)Hebe: An Order-Oblivious and High-Performance Execution Scheme for Conjunctive Predicates., , , , and . ICDE, page 1260-1263. IEEE Computer Society, (2018)Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only)., , , , and . FPGA, page 274. ACM, (2016)High-speed, fixed-latency serial links with Xilinx FPGAs., , , and . Journal of Zhejiang University - Science C, 15 (2): 153-160 (2014)Block Processor: A resource-distributed architecture., , and . HPEC, page 1-6. IEEE, (2013)Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors., , and . IEICE Transactions, 96-A (7): 1637-1641 (2013)