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Place and Route for Secure Standard Cell Design.

, and . CARDIS, volume 153 of IFIP, page 143-158. Kluwer/Springer, (2004)

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Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (6): 1146-1154 (2006)A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing., , , , , , and . DAC, page 222-227. ACM, (2005)Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment., , , , , , and . CHES, volume 3659 of Lecture Notes in Computer Science, page 354-365. Springer, (2005)Changing the Odds Against Masked Logic., and . Selected Areas in Cryptography, volume 4356 of Lecture Notes in Computer Science, page 134-146. Springer, (2006)Secure Logic Synthesis., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1052-1056. Springer, (2004)Securing Embedded Systems., , , and . IEEE Security & Privacy, 4 (2): 40-49 (2006)On the complexity of side-channel attacks on AES-256 - methodology and quantitative results on cache attacks., and . IACR Cryptology ePrint Archive, (2007)An Analytical Model for Time-Driven Cache Attacks., , , and . FSE, volume 4593 of Lecture Notes in Computer Science, page 399-413. Springer, (2007)Place and Route for Secure Standard Cell Design., and . CARDIS, volume 153 of IFIP, page 143-158. Kluwer/Springer, (2004)A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs, and . CoRR, (2007)