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A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.

K. Qiu, W. Chen, Y. Xu, L. Xia, Y. Wang, and Z. Shao. DATE, page 1057-1062. IEEE, (2018)

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Tian Qiu University of Stuttgart

Other publications of authors with the same name

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems.K. Qiu, M. Zhao, Q. Li, C. Fu, and C. Xue. IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (3): 329-342 (2014)Redesigning software and systems for non-volatile processors on self-powered devices.M. Zhao, K. Qiu, Y. Xie, J. Hu, and C. Xue. VLSI-SoC, page 1-6. IEEE, (2016)Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.F. Li, K. Qiu, M. Zhao, J. Hu, Y. Liu, Y. Guan, and C. Xue. IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (1): 15-28 (2019)BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.K. Qiu, Y. Zhu, Y. Xu, Q. Huo, and C. Xue. Microelectronics Journal, (2019)A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.K. Qiu, W. Chen, Y. Xu, L. Xia, Y. Wang, and Z. Shao. DATE, page 1057-1062. IEEE, (2018)Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors.Z. Shi, D. Zhou, K. Qiu, and J. Shu. ASAP, page 189-196. IEEE, (2019)Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM.K. Qiu, Q. Li, and C. Xue. DAC, page 106:1-106:6. ACM, (2014)Refresh-aware loop scheduling for high performance low power volatile STT-RAM.K. Qiu, J. Luo, Z. Gong, W. Zhang, J. Wang, Y. Xu, T. Li, and C. Xue. ICCD, page 209-216. IEEE Computer Society, (2016)Near threshold cloud processors for dark silicon mitigation: the impact on emerging scale-out workloads.J. Wang, J. Zhang, W. Zhang, K. Qiu, T. Li, and M. Wu. Conf. Computing Frontiers, page 4:1-4:8. ACM, (2015)Error Model Guided Joint Performance and Endurance Optimization for Flash Memory.L. Shi, K. Qiu, M. Zhao, and C. Xue. IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (3): 343-355 (2014)

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Disambiguation of "Qiu, Keni"

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A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.

Please choose a person to relate this publication to

Tian Qiu University of Stuttgart

Other publications of authors with the same name

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PUMA

Disambiguation of "Qiu, Keni"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.

Please choose a person to relate this publication to

Tian Qiu University of Stuttgart

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A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.