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A mixed signal architecture for convolutional neural networks.

Q. Lou, C. Pan, J. McGuinness, A. Horváth, A. Naeemi, M. Niemier, and X. Hu. CoRR, (2018)

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Qi Pan University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

Qifeng Pan University of Stuttgart

Other publications of authors with the same name

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.C. Pan, P. Raghavan, F. Catthoor, Z. Tokei, and A. Naeemi. ISQED, page 599-603. IEEE, (2015)Impact of interconnect variability on circuit performance in advanced technology nodes.D. Prasad, C. Pan, and A. Naeemi. ISQED, page 398-404. IEEE, (2016)A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.C. Pan, and A. Naeemi. IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 75-87 (2015)An analytical approach to system-level variation analysis and optimization for multi-core processor.C. Pan, S. Mukhopadhyay, and A. Naeemi. ISQED, page 99-106. IEEE, (2014)A Mixed Signal Architecture for Convolutional Neural Networks.Q. Lou, C. Pan, J. McGuinness, A. Horváth, A. Naeemi, M. Niemier, and X. Hu. JETC, 15 (2): 19:1-19:26 (2019)Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications.C. Pan, and A. Naeemi. CoRR, (2017)A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices.C. Pan, and A. Naeemi. CoRR, (2016)Device/system performance modeling of stacked lateral NWFET logic.V. Huang, C. Pan, D. Yakimets, P. Raghavan, and A. Naeemi. ISQED, page 215-220. IEEE, (2016)Performance modeling and optimization for on-chip interconnects in 3D memory arrays.J. Mohseni, C. Pan, and A. Naeemi. ISQED, page 252-257. IEEE, (2016)System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.C. Pan, and A. Naeemi. ICICDT, page 1-5. IEEE, (2012)

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Disambiguation of "Pan, Chenyun"

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A mixed signal architecture for convolutional neural networks.

Please choose a person to relate this publication to

Qi Pan University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

Qifeng Pan University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Pan, Chenyun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A mixed signal architecture for convolutional neural networks.

Please choose a person to relate this publication to

Qi Pan University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

Qifeng Pan University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A mixed signal architecture for convolutional neural networks.