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Circuit design techniques for increasing the output power of switched capacitor charge pumps.

, , and . CCECE, page 1-5. IEEE, (2014)

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On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)., , and . IEEE Trans. VLSI Syst., 20 (4): 770-774 (2012)A novel non-destructive readout circuit for Memristor-based memory arrays., , and . CCECE, page 1-5. IEEE, (2014)Comparative review of the TiO2 and the spintronic memristor devices., , and . CCECE, page 1-6. IEEE, (2014)Negative capacitance circuits for process variations compensation and timing yield improvement., , and . CCECE, page 1-4. IEEE, (2014)Statistical timing yield improvement of dynamic circuits using negative capacitance technique., , and . ISCAS, page 1747-1750. IEEE, (2010)NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA., , and . Integration, (2018)Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources., , , and . Integration, (2018)Design exploration for network on chip based FPGAs: 2D and 3D tiles to router interface., , and . Microelectronics Journal, (2019)Dynamic power estimation using Transaction Level Modeling., , , , , , , , and . Microelectronics Journal, (2018)On the use of a programmable front-end for multi-band/multi-standard applications., , , and . Microelectronics Journal, (2016)