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Disambiguation of "Savin, Valentin"

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Benefits and Challenges of Cloud Technologies for 5G Architecture.

, , , , , , , , and . VTC Spring, page 1-5. IEEE, (2015)

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Valentin Kamm University of Stuttgart

Prozessmodellierung für das Rührreibschweißen : Semi-analytisches Prozessmodell für das roboterbasierte Rührreibschweißen : Process modeling of friction stir welding : Semi-analytical process model of robotic friction stir welding, , , and . Werkstattstechnik, 113 (5): 183-188 (2023)

Valentin Leipe University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

 

Other publications of authors with the same name

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation., , , , and . IEEE Trans. on Circuits and Systems, 66-I (4): 1643-1656 (2019)Scheduled-PEG construction of LDPC codes for Upper-Layer FEC, , , and . CoRR, (2011)Analysis of Min-Sum based decoders implemented on noisy hardware., , and . ACSSC, page 866-870. IEEE, (2013)High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders., , , and . ICC Workshops, page 961-966. IEEE, (2017)Code-Aware Power Allocation for Irregular LDPC Codes., and . CrownCom, volume 172 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 41-52. Springer, (2016)Iterative LDPC decoding using neighborhood reliabilities.. ISIT, page 221-225. IEEE, (2007)Memory efficient implementation of self-corrected min-sum LDPC decoder., , and . ICECS, page 295-298. IEEE, (2014)Split-extended LDPC codes for coded cooperation.. ISITA, page 151-156. IEEE, (2010)Code-design for efficient pipelined layered LDPC decoders with bank memory organization., , , and . Microprocessors and Microsystems - Embedded Hardware Design, (2018)Dynamic-SCFlip Decoding of Polar Codes., , and . CoRR, (2017)