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A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry.

J. Tsai, H. Wang, Y. Chen, Y. Wei, Y. Kao, Y. Yen, P. Huang, M. Shen, and H. Chen. IEEE Trans. on Circuits and Systems, 61-II (11): 825-829 (2014)

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Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Dr. -Ing. Min Huang University of Stuttgart

Shih-Min Huang University of Stuttgart

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A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.C. Hsieh, C. Lai, G. Ke, J. Liu, and P. Huang. VLSI-DAT, page 1-4. IEEE, (2014)An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.Y. Wu, C. Lai, C. Chou, and P. Huang. ISCAS, IEEE, (2006)A UWB IR timed-array radar using time-shifted direct-sampling architecture.C. Lai, K. Tan, L. Yu, Y. Chen, J. Huang, S. Lai, F. Chung, C. Yen, J. Wu, P. Huang and 3 other author(s). VLSIC, page 54-55. IEEE, (2012)A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement.J. Tsai, S. Ko, H. Wang, C. Wang, H. Chen, and P. Huang. A-SSCC, page 233-236. IEEE, (2014)A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics.J. Tsai, S. Ko, C. Wang, Y. Yen, H. Wang, P. Huang, P. Lan, and M. Shen. J. Solid-State Circuits, 50 (11): 2533-2548 (2015)A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique.P. Lan, T. Yang, and P. Huang. IEEE Trans. VLSI Syst., 21 (1): 67-77 (2013)A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range.P. Lan, and P. Huang. IEEE Trans. on Circuits and Systems, 59-I (10): 2468-2476 (2012)A Low Cost Calibrated DAC for High-Resolution Video Display System.M. Shen, and P. Huang. IEEE Trans. VLSI Syst., 20 (9): 1743-1747 (2012)A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops.M. Shen, P. Lan, and P. Huang. IEEE Trans. on Circuits and Systems, 55-II (5): 409-413 (2008)A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.J. Tsai, H. Wang, Y. Yen, C. Lai, Y. Chen, P. Huang, P. Hsieh, H. Chen, and C. Lee. J. Solid-State Circuits, 50 (6): 1382-1398 (2015)