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Novel Technique for Testing FPGAs., , , , , , , , and . DATE, page 89-94. IEEE Computer Society, (1998)Built-In Self-Test with an Alternating Output., , , and . DATE, page 180-184. IEEE Computer Society, (1998)A Test Interface for Built-In Test of Non-Isolated Scanned Cores., , and . VTS, page 371-378. IEEE Computer Society, (2003)An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories., , and . VTS, page 95-100. IEEE Computer Society, (2008)SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms., , , , and . VTS, page 66-71. IEEE Computer Society, (2005)Leveraging Infrastructure IP for SoC Yield.. Asian Test Symposium, page 3-5. IEEE Computer Society, (2003)T1: Design for Manufacturability., and . Asian Test Symposium, IEEE Computer Society, (2005)Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA., , , and . Asian Test Symposium, page 254-. IEEE Computer Society, (1997)Design, test & repair methodology for FinFET-based memories.. ITC, page 1. IEEE Computer Society, (2014)Today's SOC test challenges.. ITC, page 2. IEEE Computer Society, (2005)