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Disambiguation of "Shu, Yun-Shiang"

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F2 : Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits

, , , , , and . 2021 IEEE International Solid- State Circuits Conference (ISSCC), page 517-519. Piscataway, IEEE, (2021)
DOI: 10.1109/ISSCC42613.2021.9365818

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Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

 

Other publications of authors with the same name

A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration., , , , and . CICC, page 157-160. IEEE, (2008)A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators.. VLSIC, page 26-27. IEEE, (2012)A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration., , , , and . J. Solid-State Circuits, 44 (9): 2356-2365 (2009)F2 : Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits, , , , , and . 2021 IEEE International Solid- State Circuits Conference (ISSCC), page 517-519. Piscataway, IEEE, (2021)A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator., , , , and . CICC, page 9-12. IEEE, (2009)An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS., , , , and . ISSCC, page 334-336. IEEE, (2019)LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators., , , , and . J. Solid-State Circuits, 45 (2): 368-379 (2010)A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering., and . J. Solid-State Circuits, 43 (2): 342-350 (2008)A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection., , and . ISSCC, page 500-501. IEEE, (2008)27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS., , and . ISSCC, page 458-459. IEEE, (2016)