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Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.

H. Xu, V. Pavlidis, X. Tang, W. Burleson, and G. Micheli. IEEE Trans. VLSI Syst., 21 (12): 2226-2239 (2013)

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TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.X. Tang, J. Zhang, P. Gaillardon, and G. Micheli. ISCAS, page 1660-1663. IEEE, (2014)Novel configurable logic block architecture exploiting controllable-polarity transistors.P. Gaillardon, X. Tang, and G. Micheli. ReCoSoC, page 1-3. IEEE, (2014)FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs.X. Tang, E. Giacomin, G. Micheli, and P. Gaillardon. IEEE Trans. VLSI Syst., 27 (3): 637-650 (2019)Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.W. Neto, X. Tang, M. Austin, L. Amarù, and P. Gaillardon. ISVLSI, page 224-229. IEEE, (2019)Physical Design Considerations of One-level RRAM-based Routing Multiplexers.X. Tang, E. Giacomin, G. Micheli, and P. Gaillardon. ISPD, page 47-54. ACM, (2017)Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.H. Xu, V. Pavlidis, X. Tang, W. Burleson, and G. Micheli. IEEE Trans. VLSI Syst., 21 (12): 2226-2239 (2013)Optimization opportunities in RRAM-based FPGA architectures.X. Tang, G. Micheli, and P. Gaillardon. LASCAS, page 1-4. IEEE, (2017)A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.J. Vieira, E. Giacomin, Y. Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P. Gaillardon. VLSI-SoC, page 160-165. IEEE, (2019)A high-performance low-power near-Vt RRAM-based FPGA.X. Tang, P. Gaillardon, and G. Micheli. FPT, page 207-214. IEEE, (2014)Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.X. Tang, E. Giacomin, G. Micheli, and P. Gaillardon. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 639-650 (2018)

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Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.

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Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.