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CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search.

, , , , and . IPDPS Workshops, page 228-235. IEEE Computer Society, (2014)

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Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms., and . ASAP, page 185-191. IEEE Computer Society, (2013)CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search., , , , and . IPDPS Workshops, page 228-235. IEEE Computer Society, (2014)Shepard: A fast exact match short read aligner., , , , and . MEMOCODE, page 91-94. IEEE, (2012)A high performance systolic architecture for k-NN classification., , and . MEMOCODE, page 201-204. IEEE, (2014)A 15-bit binary-weighted current-steering DAC with ordered element matching., , , and . CICC, page 1-4. IEEE, (2013)A multi-phase approach to floating-point compression., and . EIT, page 251-256. IEEE, (2015)A Scalable Unsegmented Multiport Memory for FPGA-Based Systems., , , and . Int. J. Reconfig. Comp., (2015)Accelerating all-pairs shortest path using a message-passing reconfigurable architecture., , , , and . ReConFig, page 1-6. IEEE, (2015)RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing., , , , and . IEEE Trans. Parallel Distrib. Syst., 27 (10): 3029-3043 (2016)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . TRETS, 9 (2): 16:1-16:19 (2016)