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Guest Editor's Introduction: Advances in Infrastructure IP.. IEEE Design & Test of Computers, 20 (3): 49- (2003)Design & Test Education in Asia., , , , , and . IEEE Design & Test of Computers, 21 (4): 331-338 (2004)A D&T Roundtable: Testing Mixed Logic and DRAM Chips., , , , , , , and . IEEE Design & Test of Computers, 15 (2): 86-92 (1998)Guest Editors' Introduction: East Meets West., and . IEEE Design & Test of Computers, 13 (1): 5-7 (1996)A Test Interface for Built-In Test of Non-Isolated Scanned Cores., , and . VTS, page 371-378. IEEE Computer Society, (2003)An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories., , and . VTS, page 95-100. IEEE Computer Society, (2008)SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms., , , , and . VTS, page 66-71. IEEE Computer Society, (2005)Novel Technique for Testing FPGAs., , , , , , , , and . DATE, page 89-94. IEEE Computer Society, (1998)Built-In Self-Test with an Alternating Output., , , and . DATE, page 180-184. IEEE Computer Society, (1998)Leveraging Infrastructure IP for SoC Yield.. Asian Test Symposium, page 3-5. IEEE Computer Society, (2003)