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Disambiguation of "Keane, John"

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A novel dynamic asset allocation system using Feature Saliency Hidden Markov models for smart beta investing.

, , , , and . CoRR, (2019)

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John Nixon University of Stuttgart

Isaac Henderson Johnson Jeyakumar University of Stuttgart

David John Cross University of Stuttgart

 

Other publications of authors with the same name

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing., , , and . J. Solid-State Circuits, 43 (2): 518-529 (2008)An array-based test circuit for fully automated gate dielectric breakdown characterization., , , and . CICC, page 121-124. IEEE, (2008)An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs., , and . ESSDERC, page 262-265. IEEE, (2012)A novel dynamic asset allocation system using Feature Saliency Hidden Markov models for smart beta investing., , , , and . CoRR, (2019)Modeling and analysis of leakage induced damping effect in low voltage LSIs., , and . ISLPED, page 382-387. ACM, (2006)5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology., , , , , , and . J. Solid-State Circuits, 52 (1): 229-239 (2017)On-chip reliability monitors for measuring circuit degradation., , , and . Microelectronics Reliability, 50 (8): 1039-1053 (2010)An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation., , and . IEEE Trans. VLSI Syst., 18 (6): 947-956 (2010)An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB., , , and . J. Solid-State Circuits, 45 (4): 817-829 (2010)A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (1): 222-229 (2016)